This invention relates generally to data communications and, more particularly, to data communications within a computer bus architecture.
The components of a computer system are typically coupled to a common bus for communicating information to one another. Various bus architectures are known in the prior art, and each bus architecture operates according to a communications protocol that defines the manner in which data transfer between components is accomplished.
The Institute of Electrical and Electronic Engineers (IEEE) has promulgated a number of different bus architecture standards including IEEE standards document 1394, entitled Standard for a High Performance Serial Bus (hereinafter xe2x80x9cIEEE 1394 Serial Bus Standardxe2x80x9d). A typical serial bus having the IEEE 1394 standard architecture is comprised of a multiplicity of nodes that are interconnected via point-to-point links, such as cables, that each connect a single node of the serial bus to another node of the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, wherein a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration and associated packet handling protocol ensures that each node receives every packet once. The serial bus of the IEEE 1394 Serial Bus Standard may be used as an alternate bus for the parallel backplane of a computer system, as a low cost peripheral bus, or as a bus bridge between architecturally compatible buses.
A communications protocol of the IEEE 1394 Serial Bus Standards specifies two primary types of bus access: asynchronous access and isochronous access. Asynchronous access may be either xe2x80x9cfairxe2x80x9d or xe2x80x9ccycle masterxe2x80x9d. Cycle master access is used by nodes that need the next available opportunity to transfer data. Isochronous access is used by nodes that require guaranteed bandwidth, for example, nodes transmitting video data. The transactions for each type of bus access are comprised of at least one xe2x80x9csubactionxe2x80x9d, wherein a subaction is a complete one-way transfer operation.
In the case of isochronous data transfers and computer systems conforming to the IEEE 1394 Serial Bus Standard, the prior art has attempted to manage the flow of data using dedicated drivers. Drivers are software entities associated with various components of a computer system and, among other functions, operate to configure the components and allow the components to be operable within the overall system. The drivers of the prior art have allowed for the transmission of video data from a digital video camera to a monitor, but have not allowed for real time video transmissions in a multi-tasking environment. In particular, the drivers of the prior art have required that a bus controller, e.g., the computer system""s CPU, listen to a data channel at the exclusion of all other processes. As data arrives on the channel, it is stored in a buffer for later transmission to a frame buffer associated with a monitor. A new listen instruction must be issued for each separate isochronous data transmission. That is, if a single transmission corresponds to data for a single scan line of the monitor, for a display of five scan lines, five separate listen instructions are required. Because the data is being sent in real time, this system requires that the processor spend all of its time servicing the isochronous data transmissions, even if no data is currently being transmitted on the bus, without servicing any other tasks. It would, therefore, be desirable to have a means and method for a more efficient management of isochronous data channels in a computer system.
A computer implemented method of managing isochronous data channels in a computer system is described. In one embodiment, the computer system conforms to the IEEE 1394 Serial Bus Standard. An isochronous channel is established within the computer system and includes a linked list of buffers. The linked list of buffers corresponds to display locations on a display which is part of the computer system. Once the linked list of buffers has been established, the computer system executes instructions which allow for the transmission of isochronous data across the channel. Each time a sender node, a video camera in one embodiment, is ready to transmit data, an interrupt is generated which causes the processor to execute instructions to manage the flow of data from the sender. The processor transfers the data transmitted by the camera to a storage location within the linked list of buffers. Ultimately, this data is transferred to a frame buffer associated with a display. This interrupt driven management allows the processor to perform other tasks when no data is being transmitted over the isochronous channel.
In another embodiment, the data transfer is DMA driven rather than interrupt driven. For this embodiment, the isochronous channel, including the linked list of buffers, is established and the process is initiated. Data transmitted by the video camera is transferred to memory locations within the linked list of buffers by the DMA hardware and then ultimately transferred to a frame buffer for display.
In yet another embodiment, the central processing unit (CPU) for the computer system establishes an isochronous channel between a sender node and one or more receiver nodes, not including the CPU itself. For this embodiment, no linked list of buffers is required as data from the sender node is transferred directly to the receiver node.